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Description:
The 3D7225 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 700ns. The
input is reproduced at the outputs without inversion, shifted in
time as per the user-specified dash number. The 3D7225 is TTL- and
CMOS-compatible, capable of driving ten 74LS-type loads, and
features both rising- and falling-edge accuracy.
The all-CMOS 3D7225 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It
is available in bare die and wafer format for maximum integration
and size reduction in today’s complex hybrid circuit and
Multi-Chip-Module applications.
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Features:
- All-silicon,
low-power CMOS technology
- TTL/CMOS compatible
inputs and outputs
- Low ground bounce
noise
- Leading- and
trailing-edge accuracy
- Delay range:
0.75ns through 3500ns
- Delay tolerance:
2% or 0.5ns
- Temperature
stability: ±2% typical
- VDD stability:
±1% typical (4.75V-5.25V)
- Minimum input
pulse width: 30% of total delay
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