The Benefits of Using Bare Die
Designers of space-constrained systems face the challenge of determining how to incorporate expanding functional needs into reduced spaces in a timely and cost-effective manner. For many handheld, portable, and other small form factor products, silicon packaging has become the major size-limiting element of their design layout. The conversion from standard semiconductor packaging to unpackaged die provides the system designer with opportunities for more efficient use of limited space. At the same time, bare die implementation affords improved electrical performance, better signal integrity, and higher levels of integration with reduced weight and height. These benefits allow designers to overcome the challenges of small form factor applications.
Mintech Semiconductors provides products that can be used in two forms of die assemblies:
Standard bare die for wire bond applications Die for bumped flip-chip applications
Both assembly formats offer size improvements over traditional packaged product outlines.
As shown in the figure (below), the implementation in die form of a standard dual Phased Locked Loop can reduce space consumption by greater than 50%.
Die vs. Package Size Improvements
The implementation rate of die products is rapidly increasing as a result of both application form factor needs and system performance improvement requirements. The main customer application drivers in the migration from packaged semiconductor die to wire bond or bumped flip-chip die include:
Electrical performance
The lower inductance and capacitance of bare die is important in analog, RF, and power applications. Signal propagation and power/ground distributions are also improved.
Size and weight
Improvements vary based on the current packaging in use; flip-chip can reduce the function footprint by 70% to 90% of the current.
Reliability
The reduced number of interconnects with die use, leads to improved reliability. The typical packaged part has three connection points per I/O. Compare this with only two for wire bonds and a single solder joint with flip-chip.
Lower cost of ownership
This is most notable in high volume applications where density is required and high yield silicon is implemented. The lower cost of ownership takes into consideration substrate, assembly, system test, equipment utilization, rework, and increased product value. In addition, the cost of a die product is typically lower than the package equivalent. Process simplification - With bumped die and flip-chip processing, the assembly flows are streamlined by reducing the number of process steps.
These die advantages promote higher levels of integration using existing mature products, lead to increased functionality per square area, and reduce costs. Additionally, performance improvements are achieved with no additional cost penalty. Integrating die for SiP (System-in-Package) solutions provides a benefit over both standard package solutions and SOC (System-on-Chip) solutions. As design cycle time requirements continue to shorten and product time to market becomes increasingly important, die for SiP solutions finds greater utility in meeting the designer's needs.
Application support for die
Mintech Semiconductors Ltd have a close working relationship with our
franchised line manufacturers. Die datasheets and product electrical specifications are available through our
contacts or through our
web site login and include:
- Die dimensions
- Bond pad details
- Bond pad maps
- Die backside detail
- Bond pad pin out detail
- Electrical specifications
We can also help you to select die products, evaluate assembly options and provide assistance in selecting sources for bump manufacture. We can provide all die information to support bump manufacture.
For more information please
contact our sales department.